This application relates to the subject matter, of U.S. application Ser. No. 09/839,954 filed by Hirohide Sugahara, et al. on Apr. 19, 2001 and U.S. application Ser. No. 09/785,071 filed by Hirohide Sugahara, et al. on Feb. 14, 2001.
The present invention relates generally to computer networking, and more particularly to sending notification over a computer network.
In a computer network made of interconnected processors, memories, input/output and/or other devices, these processors, memories, input/output and/or other devices may need to notify each other about certain events. For example, an interrupt signal may be sent from one device to a processor, indicating that an event has occurred and that the processor receiving the interrupt should suspend its current task to service a designated activity associated with the event. Interrupts are usually sent through interrupt request lines, or IRQs. The IRQs are hardware lines over which a processor receives interrupt signals from devices or other processors. There may be multiple IRQs associated with a processor, and each is routed to one or more devices in the computer network. When a processor receives an interrupt signal, it takes a specified action. The processor may choose to ignore the interrupt, or it may try to identify the source of the interrupt and then invoke an interrupt handler routine to respond to the interrupt. Typically, when an interrupt is sent over an IRQ, no information on the particular device which sent the interrupt is provided. The processor receiving the interrupt would have to poll the devices to which the interrupt line is routed in order to determine which device actually sent the interrupt. When the initiator of the interrupt signal is an intelligent device such as a central processing unit, it can send a more sophisticated notification such as an interrupt message to another processor. The processor receiving the interrupt message can determine the source of the notification and can obtain other information such as status or error information of the initiator of the notification by reading the interrupt message.
Traditionally interrupt messages are sent over a computer network using a technique called message passing. A common use of message passing is for communication in parallel computing, where a process running on one processor may send a message to a process running on the same processor or another processor. In a computer network where message passing is utilized, each processor has its own private memory. When a local processor sends a message to a remote processor using message passing, a block of memory is read locally and written remotely. This operation requires that sufficient memory is available to buffer the message at its destination and at intermediate nodes. Software run by the sending processor prepares data to be sent in its local memory and the data is transferred to a prepared memory buffer associated with the receiving processor. Before the sending processor transfers the data through the network, it needs to check with the receiving side for the address to store the data. These procedures are time consuming and make message passing inefficient when dealing with a message as small as a conventional interrupt message.
Therefore, there is a need for a system and a method that allows a processor coupled to a computer network to send an interrupt message over the network to another processor without going through the aforementioned procedures.
The present invention comprises a method and system for fast delivery of an interrupt message from a first processor to a second processor in a computer network.
In one embodiment of the present invention, the first and second processors are coupled to a first and second Peripheral Component Interconnect (xe2x80x9cPCIxe2x80x9d) buses, respectively. A first and second PCI network adaptors are used to couple the first and second PCI buses, respectively, to the computer network. The first and second PCI network adaptors include functional units to facilitate a memory-mapped write on the first PCI bus to be bridged to the second PCI bus through the computer network.
One embodiment of the present invention allows the first processor to very quickly send a processor-to-processor interrupt along with queuing a four byte or eight byte message using only a single-memory-mapped PCI write to a doorbell address range associated with the second processor. A PCI write on the first PCI bus to the doorbell address range associated with the second processor is accepted by the first PCI network adaptor and is routed to the second PCI network adaptor. The second network adaptor recognizes the PCI write as a write to the doorbell space and cause an IRQ be asserted for the second processor and the queuing of the write data into one of a circular buffer.